Synopsis Synthesis Instructions
- Create a vhdl directory (mkdir vhdl)
- Copy the following files (on UNIX use your right mouse button to do
this):
.synopsys_dc.setup
.synopsys_sge.setup
.synopsys_vss.setup
- Synthesis: Run the Synopsys tool:
- %> design_analyzer &
-
- In menu FILE, choose Analyze and select the vhd files to synthesize
(*_ent.vhd and *_arch.vhd).
- The first time you must click on "Create New Library if it Doesn't
Exist" in the "Analyze File" dialog box.
- Elaborate
- Click on the symbol generated by the Elaborate command
- Select menu Tools/Design Optimization
- Select menu Setup/Command Window
- Write in the command window: replace_fpga -force
- Save as xnf -> *.sxnf
- syn2xnf *.sxnf -p 5210pq208-6)
- Go to project directory and copy the xnf file
- Create WIR file:
%> xnf2wir *.xnf
- Create schematic file (and symbol):
%> viewgen *.[wir] [-makesym]
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Last updated: January, by Alex Bänninger.
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