As far as self-replication is concerned, our goal was met in most respects. Our self-replication mechanism is indeed capable of generating multiple copies of our artificial cells from the description of a single such cell. The mechanism allows for cells of any given size, and thus capable of executing any given task. The only compromise we had to accept was the use of an external source for the configuration of the cells. As we mentioned in the introduction, ideally it should be the cells themselves which generate and control the replication process. In our case, the replication process is indeed controlled by the dedicated hardware integrated in our FPGA, but the configuration bitstream is generated outside the circuit itself and not by the cells. The development of such an "ideal" system remains a future research goal for the Embryonics project.
As far as the self-repair mechanism is concerned, the results are not quite as close to optimum. Notably, the self-test mechanism falls somewhat short of the ideal outlined in the introduction. The constraints of biological inspiration, coupled with the need to minimize the hardware overhead, proved too strong to allow on-line self-test of more than a relatively small part of the circuit. However, our system is indeed able to transparently detect faults on a large part of the circuit 36 through off-line self-test at configuration.
On the other hand, the self-repair mechanism itself fits our requirements remarkably well: it allows for the repair of a considerable number of faults (the exact coverage depends, of course, on the number of spare elements allotted to the array) and is indeed capable of activating the self-repair at the cellular level through its global KILL signal. While the self-repair process is not guaranteed to occur transparently to the user, an effort was made to minimize the time it requires. In addition, our system actually surpasses our requirements by introducing the very useful feature of programmable redundancy, which allows the user to determine the amount of logic to be "sacrificed" for additional self-repair capabilities.
As a final consideration, we will mention that the hardware overhead required by the introduction of self-repair and self-replication is of approximately 50-70% 37 compared to the basic version of MuxTree. Considering the extremely fine grain of our FPGA, we are very satisfied by this figure, which includes all the additional logic necessary for self-replication, self-test, and self-repair, as well as the control logic required to handle these processes.
Chapter 2 is meant to provide some background material for the Embryonics project in general. As such, I obviously cannot claim sole credit for its development: in particular, the epigenetic and phylogenetic axes are not really within the scope of my research. As far as the ontogenetic axis is concerned, its development was a collective effort on the part of a small group of people, including myself. I feel I have contributed in a substantial way to its development, and in particular to the definition of the 3-layer system (organism, cell, molecule) which is the core of our vision of ontogenetic hardware. Obviously, my contribution was mostly centered on the definition of the requirements and constraints of the molecular layer.
Chapter 3 contains what is probably my most original contribution, at least from a conceptual standpoint: the self-replication mechanism. When I first approached the problem, the state of the art for self-replicating machines was represented by Langton's loop, a structure obviously ill-suited to a hardware realization. In a first phase, I therefore had to improve the state of the art by designing a novel self-replicating loop which, while not directly designed for hardware implementation, represented an important step forward in the development of computationally-useful self-replicating structures 38. The need to design new self-replicating structures also led to the development of a novel software tool (see Appendix A) which provides a novel approach to the design of complex cellular automata. In a second phase, I had to develop an hardware mechanism capable of implementing self-replication in our FPGA. This process, which led to the integration of the cellular automaton in the MuxTree array, required considerable original thought since, to the best of my knowledge, such a mechanism is quite unique.
Chapter 4 deals with the hardware implementation of the self-test and self-repair mechanisms on the MuxTree FPGA. The actual implementation, in the form of a digital logic circuit programmed into a Xilinx FPGA (see Appendix B), was entirely my own work. As far as the architecture of the system is concerned, determining the original features of the design is less straightforward. The programmable function and the switch block of the MuxTree element predate my arrival in the laboratory, and while I was forced to introduce some minor modifications, I cannot claim authorship. On the other hand, the configuration mechanism is entirely my own work. For self-test and self-repair, I was forced to rely on standard techniques, mostly because the size of the elements did not allow complex mechanisms. However, while the test and repair strategies are not original (comparison, test patterns, spare columns, etc., are all "standard" techniques), it was, to the best of my knowledge, the first attempt to integrate on-line self-repair in a circuit as fine-grained as MuxTree. An important effort was thus required in order to select which approaches were viable given our constraints. I also had to integrate the mechanisms into the existing hardware with a major effort towards minimizing the additional silicon. This effort was remarkably successful in the case of the self-repair mechanism (which exploits much of the logic already in place). A notable original achievement was also the idea of exploiting the cellular automaton to configure the degree of fault tolerance (to the best of my knowledge, this feature is also unique, at least where FPGAs are concerned).
The net result of this approach is that MuxTreeSR, as a whole, would probably not be a commercially viable product. However, this consideration does not preclude the possibility of adapting the particular mechanisms we developed in this project to commercial systems. In this section, we will analyze the strength and weaknesses from a commercial standpoint of three separate parts of our system: the MuxTree FPGA, the self-replication mechanism, and the self-repair approach.
On the other hand, the structure of MuxTree, designed to efficiently implement binary decision trees and diagrams, could be an interesting advantage for applications which can be easily described as logic functions (e.g., many state machines and control applications). A considerable number of software packages, both commercial and academic, are capable of deriving minimized binary decision diagrams from a given logic function, and such diagrams can then be used to trivially generate the configuration for a MuxTree array. Since many such control-applications are not usually speed-critical, MuxTree's shortcomings in this respect become less important.
These considerations, however interesting and, in a sense, useful, should not be given too much emphasis: MuxTree was not designed to be and is not likely to become a commercial product in the foreseeable future. Even if it has the potential to become an useful programmable logic device outside of the Embryonics project, it does not, by itself, provide enough unique advantages to be able to compete with the latest generation of FPGAs. Moreover, adapting it for a commercial release would require a major effort on the part of a team of developers, a task outside the competence of our laboratory. In particular, the development of the software tools which would be indispensable to achieve commercial success, and which are basically non-existing at this stage, is an effort beyond our possibilities (and, to a large extent, outside of our interests).
At first sight, self-replication is the feature of our system which is most closely related to the particular requirements of the Embryonics project, and consequently the least likely to be of use outside of our project. However, if we look at our mechanism without considering the biologically-inspired cellular level, we can see that self-replication is an extremely efficient approach to the implementation of arrays of identical elements of any given structure.
We have mentioned that FPGAs appear to become more and more application-specific, and it is therefore not difficult to imagine FPGAs designed specifically to implement arrays of identical processing elements, structures which are very well-suited for a wide number of applications: SIMD (Single-Instruction Multiple-Data) parallel processing, bit-slice architectures, etc. Considering the complexity of such applications, and consequently the difficulty of configuring FPGAs to implement them, the possibility of automatically obtaining two-dimensional arrays of processing elements from the configuration bitstream of a single such element could become a very powerful advantage.
From a manufacturer's point of view, our system is probably too powerful: on-line self-test and self-repair are not yet enough of a priority to warrant the hardware overhead required by such systems. On the other hand, there is no reason why our mechanism might not be simplified in order to more closely fit the requirements of the commercial world. In particular, we feel that a simplified version of our system might very well be adapted to achieve self-repair at fabrication (a more likely requirement for FPGA manufacturers) with a more than acceptable overhead.
In the design of such a system, several modifications would be needed. In the first place, the self-test mechanism would have to be completely redesigned, both to be adapted to the new architecture of the elements and to take advantage of the possibility of operating off-line. While the test of the configuration register would easily be adapted to most new architectures, the test of the functional part and of the connections would have to be modified depending on the layout of the element.
As for the self-repair mechanism, very little modification would be required, as it already supports static reconfiguration (rerouting of the connections before configuration in case of permanent faults). In order to adapt it to a new architecture for repair at fabrication, the only major alteration would be a simplification: the removal of the logic required for dynamic reconfiguration (rerouting of the connections and shift of the configuration whenever a fault is detected during operation).
Of course, the programmable redundancy of our system depends on the homogeneity of the array and on the self-replication mechanism, and would therefore be lost in a commercial system which is not likely to implement these two features. Nevertheless, the simplicity of the system, coupled with its versatility, could be of interest to FPGA manufacturers, even in a simplified form.
In the phylogenetic axis, where the design of Firefly  demonstrated the feasibility of hardware evolution, we are currently studying the application of evolutionary strategies to the design of hardware systems such as, for example, fuzzy controllers. As for future developments of evolutive hardware systems, we are investigating the feasibility of open-ended undirected evolutionary strategies, that is, systems which evolve not towards a precise, user-defined goal, but independently. Such an approach is undoubtedly a much closer approximation of natural evolution.
The epigenetic axis is advancing into the application phase, where we are trying to apply our algorithms to the solution of real-life problems and for the control of autonomous robots. An interesting possible evolution along this axis would be the creation of neural networks capable of continuous learning, that is of learning new behaviors (and consequently of adapting their structure) not only during a dedicated learning phase, but also while operating. Obviously, such systems would much more closely approach the behavior of biological neural networks than conventional ANNs.
On the ontogenetic axis, to which this thesis belongs, even if a considerable amount of work remains, we can begin to glimpse a possible closure. The next major step in the development of this axis is the design of the BioWatch 2001, an extremely complex machine which we hope to present on the occasion of the Expo.01, a major scientific and cultural event which will take place in the year 2001 in Switzerland. The function of the machine will be that of a self-replicating and self-repairing watch, implemented through macroscopic versions of our artificial cells and molecules (Fig. 5-1).
Once this improvement is in place, the development cycle for MuxTree will approach its end. We might consider adding a few extra features, for example, in order to achieve true self-replication (as mentioned above in section 5.1), but such additions are not likely to improve the circuit's performance in any significant way. At this stage, we might well be interested in designing a VLSI chip containing an array of MuxTree elements.
The closure of development of MuxTree will not, however, necessarily mean the end of research in the ontogenetic axis. In fact, with a set of mechanisms in place capable of realizing an ontogenetic machine, we could try to consider a possible merging of the three axes of the POE model (Fig. 5-2). For example, following von Neumann's sequence of self-replicating machines, we could imagine replacing the functional part of the MuxTree element with a neuron-like structure, thus joining the epigenetic and ontogenetic axes.
For the moment, this kind of convergence is fairly remote, and a subject of speculation only. On the other hand, the work presented in this thesis is an interesting first step in the development of such advanced systems. By introducing features such as self-replication and self-repair, we hope to have shown that it is possible to draw inspiration from biology in the design of digital circuits, and indeed that bio-inspiration can lead to the development of novel and powerful architectures.
36.We cannot provide an accurate estimate of the fault coverage provided by our system, as MuxTree is a circuit in constant evolution still far from its final implementation.
37.Again, an accurate estimate is difficult, both because MuxTree is constantly evolving and because our only physical realization (described in Appendix B) relies on programmable logic (Xilinx FPGAs) to implement our elements. A more accurate estimate would be possible if MuxTree were to be implemented as a VLSI chip.
38.The gratifying number of references to this work in the literature seems to indicate that the automaton, designed as an intermediate step, has nevertheless a certain intrinsic interest.